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TS201 LVDS timing

Question asked by apomerants on Dec 28, 2014
Latest reply on Mar 25, 2015 by MaheshN


We are using the TS201-050 in our video card.

The TS201 recieves/ sends its video information via its LVDS links towards a FPGA.

The DSP receives  a 108MHz SCLK, its core is running at CCLK of 4x108=432Mhz, and the LVDS links run at CLKO/ I of 108Mhz .

In a new version of the card we have changed the FPGA from Spartan3 to Spartan6_low voltage.

The data link doesn't work for us any more at the FPGA side.

Seems that one can not use a specific delay board on the low voltage Spartan.

I saw on the Anomaly TS201 paper that min hold/setup time can reach 1.1nS for our clock rate (9.2nS)

This is probably a problem for the FPGA.

Can I control this delay?

I was looking for a 90 or even 180deg shift at the CLKO phase but with no luck...

It is a bit to late so solve it by on board trace prolonging...


Any idea how to overcome this problem will be appreciated.

If you have an application note of how to match timings between the DSP and the FPGA please send me



Happy new year