we are planning a small DSP board using the ADAU1701.
Features should be:
internal ADC (2 channel)
internal DAC (4 channel)
external S/PDIF receiver (maybe with transmitter to)
external DAC (2 channel)
Now it comes to the clocking.
Lets say, we are using i.e. a WM8804 as the S/PDIF receiver, then this will be the clock master MCLK for the whole system. (This IC got a clock switchover for locked/unlocked PLL from recovered S/PDIF data)
When using a 12.288Mhz with the WM8804, this will be our master clock when no digital signal is provided. When feeding in a signal to the S/PDIF, we will have 12.288MHz with 48kHz input and MCLK set to be 256*fs, as well as at 96kHz input and MCLK set to 128*fs for feeding the rest of the system. When feeding in 44.1kHz, there will be 11.2896MHz (256*fs), so the DSP will run ~8% slower. As i'd read in the threads here, this would be no big deal but what about some time coefficients within the DSP code?
So now there is a problem, that i cant set the ADAU PLL to be 128*fs (when running at 48kHz)
So it should be like: 96kHz fs and 256*fs = 24.576MHz (from WM8804), the PLL of the ADAU1701 should then be set to 256*fs as well (and running in double-rate).
But there also is a fundamental question, can i feed different sample rates into the ADAU1701 with fixed system-sample rate?
I mean, having the ADAU1701 running internally at 48kHz, can i input signals with 96/192kHz, i guess not. Will it work the other way? (Running the ADAU1701 at 96kHz internally and feeding in digital signals with fs<=96khz)
Lets say i want to be able to input 32-96kHz into the system, then the best (only) way to do is to use an ASRC like the AD1895/6?
Im a bit confused about all this.