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AD7441A - ADC sampling phase control: Auto adjustment algorithm ?

Question asked by Vid123 on Oct 28, 2010
Latest reply on Oct 29, 2010 by DaveD

Hi all,

 

Is there any suggestion, or program flow, or some thing that has been done to avoid the 'invalid sample time' as mentioned in the HW manual (rev J section 3.5 - page 40-41) ?

 

Over all our board works good! However,  this obviously depends on input setup (cables, source quality, etc..) and somtimes we experience the 'sample jitterring' at high frequency

 

TIA,

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