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Output timings of ADV7181D between LLC and Px outputs.

Question asked by Tamu on Dec 25, 2014
Latest reply on Jan 20, 2015 by GuenterL

Hello,

 

I have questions about output timing of ADV7181D between LLC and Px outputs.

 

First, I evaluated the timing between LLC1(27MHz) and 8bit I/F.
I used script ":AUTODETECT CVBS IN NTSC/PAL/SECAM, 8-Bit 422 encoder:" on attached file "ADV7181D_ADV7181D@_ADV7341-VER.1.0c.txt".
It seems that the timings are met with Data Output Transition Time (T11 and T12) on the datasheet.
Please refer attached file "LLC27MHz_8bit_mode.TIF".

 

Next, I evaluated the timing between LLC2(13.5MHz) and 16bit or 20bit I/F.
I used script ":AUTODETECT CVBS IN NTSC/PAL/SECAM, 8-Bit 422 encoder:".
And I changed following registers.
  LLC_PAD_SEL[2:0] address 0x8F[6:4] = 101 (Output LLC2 on LLC pin)
  OF_SEL[3:0] address 0x03[5:2] = 0001 or 0010 (20bit or 16bit @ LLC2)
It seems that the timings are NOT met with Data Output Transition Time (T11 and T12) on the datasheet.
Please refer attached file "LLC13_5MHz_16_or_20bit_mode.TIF".

 

Questions:
  Why aren't the output timings met with Data Output Transition Time (T11 and T12)?
  Do you have other output timing specification with LLC2(13.5MHz) and 16bit or 20bit I/F?

 

Thank you!
Best regards.

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