I need to setup the AD9361 into CMOS mode and I am using the no-os software and AC701 HDL design as my base. I have only modified the axi_ad9361_dev_if component in the AD6391 core. I modified it so that the rx and tx signals are single ended instead of differential, made the data 12 bits wide instead of 6, updated the delay write and delay read interfaces the delay_addr signal can select all 12 data bits and frame signals to digitally tune out the delays. Now I think I am ready to modify the software to go along with the HDL mods.
Am I missing anything that I need to do in the HDL?
Where in the software do I need to make changes to make sure that it digitally tunes the extra 6 bits for rx and 6 bits for tx that I have now added to the interface. Also, do I need to make any other mods since this code was really designed for LVDS mode?
Assuming I don't have a way to check the tx/rx data to/from the AD9361 can I tell from the console output if the spi interface is working properly?