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AD9102: help with /TRIGGER programming

Question asked by tkutscha on Dec 18, 2014
Latest reply on Jan 16, 2015 by larrywelchusa

Hi All,

 

I'm having difficulty setting up the AD9102 to output a burst of DAC values from the SRAM every time the /TRIGGER signal goes low.

 

The basic operating conditions are the following:

  • CLKP/CLKN input is running continuously at 50MHz
  • /TRIGGER signal has a falling edge every 10us (100KHz frequency, low about 5% of the time)

 

My goal is to have 8 values from the SRAM (addresses 0x6000-0x6007) that "burst" out of the AD9102 every time the /TRIGGER signal goes low.

 

Here is my C code to do so:

 

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x00002004); /* SPICONFIG - reset */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x00000000); /* SPICONFIG */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x000101C7); /* POWERCONFIG */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x00020000); /* CLOCKCONFIG */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x00030000); /* REFADJ */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x00070000); /* DACAGAIN */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x00080000); /* DACRANGE */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x000C000A); /* DACRSET */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x001E0000); /* PAT_STATUS - STOP */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x001D0001); /* RAMUPDATE */

 

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x001F0001); /* PAT_TYPE - finite */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x00200000); /* PATTERN_DLY */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x00258000); /* DACDOF - max negative */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x00270000); /* WAV_CONFIG - SRAM values */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x00280111); /* PAT_TIMEBASE */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x0029000A); /* PAT_PERIOD */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x002B0001); /* DAC_PAT - 1 time */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x002C0001); /* DOUT_START */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x002D0010); /* DOUT_CONFIG */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x00318000); /* DAC_CST */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x00354000); /* DAC_DGAIN 0x400=1x */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x00370007); /* SAW_CONFIG */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x003E0100); /* DDS_TW32 */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x003F0000); /* DDS_TW1 */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x00430000); /* DDS_PW */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x00440002); /* TRIG_TW_SEL */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x00450003); /* DDS_CONFIG */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x00470000); /* TW_RAM_CONFIG */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x005C0000); /* START_DELAY */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x005D0000); /* START_ADDR (<<4) */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x005E0070); /* STOP_ADDR (<<4) */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x005F0001); /* DDS_CYC */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x001D0001); /* RAMUPDATE */

 

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x001E0004); /* PAT_STATUS - MEM_ACCESS ON */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x001D0001); /* RAMUPDATE */

 

SPIbusSet(SPIBUS_DEV_AOM_DAC,0x60001000);

SPIbusSet(SPIBUS_DEV_AOM_DAC,0x60010000);

SPIbusSet(SPIBUS_DEV_AOM_DAC,0x60022000);

SPIbusSet(SPIBUS_DEV_AOM_DAC,0x60030000);

SPIbusSet(SPIBUS_DEV_AOM_DAC,0x60043000);

SPIbusSet(SPIBUS_DEV_AOM_DAC,0x60050000);

SPIbusSet(SPIBUS_DEV_AOM_DAC,0x60064000);

SPIbusSet(SPIBUS_DEV_AOM_DAC,0x60070000);

 

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x001E0000); /* PAT_STATUS - MEM_ACCESS OFF */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x001D0001); /* RAMUPDATE */

SPIbusSet(SPIBUS_DEV_AOM_DAC, 0x001E0001); /* PAT_STATUS - RUN */

 

If I run this code, I get the following on the oscilloscope:  (blue is DAC output, yellow is /TRIGGER signal)

NewFile6.bmp

Great!  this is what I was looking for, except for a significant delay from the falling edge of /TRIGGER to the output.

Now, if I zoom out, I get the following:

NewFile7.bmp

Wait a minute! I get only one "burst" of DAC output.  Additional falling edges on /TRIGGER don't cause additional output bursts.

 

If I zoom out even further, I get the following:

NewFile8.bmp

It looks like I get more bursts of DAC output, but only every 65536 CLKP/CLKN edges.  Seems we have a 16-bit free-running counter in the ad9102 that isn't getting reset/zeroed-out by the /TRIGGER signal.

 

Two questions:

  1. How do I change the register settings to generate a burst of DAC outputs from the SRAM every time the /TRIGGER signal goes low?
  2. How do I minimize the delay between the falling edge on the /TRIGGER signal to the first output DAC value?

 

I find the documentation very confusing, so thanks for any input you might have on this.

 

Thanks!

Tim

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