Recently， I‘m working on the KC705 of xilinx, and i wanna to design a data acquisition system in the Vivado environment.Has any guys done something like this ?
Please share your ideals and experience here !
There was already created a reference design for AD9467-250-EBZ on KC705 (hdl/projects/ad9467_fmc/kc705 at master · analogdevicesinc/hdl · GitHub) - the project can be built using Vivado 2014.2.
The no-OS software is also compatible with this project (no-OS/AD9467-FMC-EBZ at master · analogdevicesinc/no-OS · GitHub).
Thank you! It has worked on the Vivado2014.2, so as in the SDK.
But, here i have some questions:
1)I want to design a data acquisition system which can store massive data(>8MB) without any data being lost. Do you have any good ideals?
2)Can i change the "adc_data[15:0]" of the AD9467 IP core to data bus like axis_s2mm?
1. I think that it should work without modifying the design. Using AXI DMAC, multiple transfers can be queued (Register Map [Analog Devices Wiki]) so you can modify the adc_capture() accordingly (no-OS/cf_ad9467.c at master · analogdevicesinc/no-OS · GitHub).
2. The short answer is yes.
Do you mean that i should replace the "axi_ad9467_dma" IP core with the "axi_dmac_0" IP core ? And then use the multiple transfers function ?
I find the "axi_dmac_0" IP core has the Cyclic mode , and so as the "axi_ad9467_dma" IP core , I can change the state in the Vivado Giagram, so i want to know whether the "axi_ad9467_dma" IP core can work in the Cyclic mode so that i can process the data steam.
Here are some pictures of the design.
I don't think that changes are required to the HDL design. Just try to modify the software so it configures multiple transfers.
I know what you mean. But is there any example to show the multi-thransfer mode, or some documents to explain the IP core in details?
Did you try this?
Thank you ! The codes must be helpful. But before i test the DMA which is initialized in the multiple transfer mode I come across another problem! I can't get the right wave data from the DDR3 when the DMA is unchanged in the vivado and the SDK, while it works in the XPS and SDK, so i wanna to know how the data been stored in the DDR3?
Is there any way to initialize the DMAC ip core so that it can works under the interrupt mode? And whether the function in the "xaxidma.c" file can be used to initialize the DMAC which has the registers map as: Register Map [Analog Devices Wiki] ?
It does work on interrupts -- may be only under Linux -- can you check the drivers? This part may be different on no-OS. You will have to wait for Dragos to reply, he is the expert.
Thank you !
Could you show me some ways how can i create my own ip core in the Vivado? I come across some problems in the data acquisition system design, and it's a little hard for me, i don't think i can adhere to the present without your help,so thank you and Dragos and any others given me a hand!
Someone said that multiple transfer should work in the interrupt mode, but the "irp" of the axi_ad9467_dma core doesn't connect to the sys_concat_intc,so i'm confused how to initialize the dma core in the SDK. I know you are the expert about this, so i need your help to solve my puzzle.
The axi_ad9467_dma's interrupt signal is connected to bit 10 of the interrupt controller (sys_concat_intc). You did not see this, because the connection is made on the system_top.
As far as I know, the no-OS software does not have an interrupt handling routine, so you need to make that yourself.
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