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BF537- SDRAM signal integrity problem

Question asked by ali on Oct 27, 2010
Latest reply on Nov 9, 2010 by CKPATEL



We had our new design based on bf537 stamp design. We tried to make sure that our board is in compliance with all the check-lists and designer notes.

We also performed the IBIS modeling and simulation to verify that all signals pass the required timings and over-shoot undershoots etc.


The results with SDRAM were all ok with 50 ohm termination in series to the Data pins (SDRAM side), 50 Ohms in series on clk_out (SDRAM side).

But when the boards came out of fab and we tested them. I could see the data bus waveforms were clean enough but the data signals (pulses) occasionally would wave up a certain offset and then back to 0 offset. So i though maybe its because of reflections that the signal adds up to the reflected signal and attains a certain offset. Hence the RAMs didnt work even at lowered bus speeds.


On this assumption i removed the terminations, and the signals were all good and  RAMs started working at full speed.


What could have gone wrong ? or there is always a chance of error even after IBIS modeling. We made sure that our track impedences are 50 ohms.


kindly point me to IBIS modeling tutorial so i can verify that i didnt miss anything in that phase.