I have been looking into synchronizing multiple AD9129 chips clocked at 2.5 GHz. I will have up to 16 chips using multiple FPGAs to synchronize, but the synchronization procedure seems to be laborious for more than two DAC chips. From the synchronization procedure described in documentation, you need to reset FIFO read and write counters to get two chips synchronized at the divide clock (DCO=2.5GHz/4=625MHz) level. To get the two chips synchronized at the DACCLK level (2.5 GHz), the procedure seems very user-in-the-loop. It seems like you need to align the SYNC output using a high speed o-scope. I would like to have an external FPGA accept the 16 SYNC outputs from each DAC to align that way, but I don't think that's possible. I would need the FPGA clocked at 2.5 GHz, which is impossible to achieve. What am I missing?
I have seen the documentation for the AD9739 for multiple chip synchronization, and it is really what I want to achieve. However, the AD9739 has 10 dB worse SFDR in mix-mode compared to the AD9129.