we are designing a board with an AD9253 and an FPGA that receives data drom the ADC. The FPGA takes also care about setup of the ADC via SPI. The ADC is running with a sampling rate of 40MHz and should deliver data in the 12-Bit One-Lane mode.
The ADC obviously reacts correctly on the setup, because FCO is framing 12 Output bits, while default mode would be 16-Bit output mode.
Our first attempt is to read the different output test modes, but we do not see the data as stated in the data sheet.
When we use the "Mixed frequency" mode, the output pattern should be: 1010 0011 0011.
What we see is the pattern 1010 0001 1001. The strange thing is that these are the first three nibbles of the output pattern, when using the 16-Bit mode. The complete pattern than would be 1010 0001 1001 1100.
The same happens, when using the "1 x sync" pattern. The expacted pattern is 0000 0011 1111, but we see the pattern 0000 0001 1111, again representing the first three nibbles of the same pattern in 16 bit mode.
1. Is there anything in the settings that can cause this behavior?
2. Is there any known bug?
Thanks for your help.