AnsweredAssumed Answered

FMCOMMS3 crystal osc. doesn't work (no-os implementation)

Question asked by labianco on Dec 12, 2014
Latest reply on Dec 17, 2014 by labianco

Guys,

 

I am working with an AC701 dev kit, supplied no-os drivers, and FMCOMMS3 eval kit. Since I have worked with this FMCOMMS3 unit, it never seemed to work correctly using the onboard oscillator.  To get it to work, I had to remove the onboard oscillator and add the capacitor in the schematic and attach a signal generator to the ref clk input.  I have developed my own custom board that contains a AD9361 and it uses the same onboard oscillator approach as the FMCOMMS3.  This has led me back to trying to figure out why my current FMCOMMS3 unit is not working. I took the cap off and put the oscillator back on and below are my no-os console outputs and initialization settings:

 

Thanks,

Nick

 

/* Reference Clock Control */
0, //xo_disable_use_ext_refclk_enable *** adi,xo-disable-use-ext-refclk-enable
{8, 5920}, //dcxo_coarse_and_fine_tune[2] *** adi,dcxo-coarse-and-fine-tune
0,  //clk_output_mode_select *** adi,clk-output-mode-select

 

 

Entered Main!
Enabled Xilinx Cache
Assigned GPIO Parameters
Set up GPIO
Initialized SPI Interface
ad9361_reset: by GPIO
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_setup
ad9361_set_dcxo_tune : coarse 8 fine 5920
ad9361_set_trx_clock_chain
ad9361_bbpll_set_rate: Rate 983040000 Hz Parent Rate 40000000 Hz
Calibration TIMEOUT (0x5E, 0x80)
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 245760000 Hz Parent Rate 983040000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 122880000 Hz Parent Rate 245760000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 122880000 Hz Parent Rate 122880000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 30720000 Hz Parent Rate 30720000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 30720000 Hz Parent Rate 30720000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rssi_setup
ad9361_auxadc_setup
ad9361_rf_port_setup : INPUT_SELECT 0x3
ad9361_pp_port_setup
ad9361_auxdac_setup
ad9361_auxdac_set DAC1 = 0 mV
ad9361_auxdac_set DAC2 = 0 mV
ad9361_auxadc_setup
ad9361_ctrl_outs_setup
ad9361_gpo_setup
ad9361_set_ref_clk_cycles : ref_clk_hz 40000000
ad9361_txrx_synth_cp_calib : ref_clk_hz 40000000 : is_tx 0
ad9361_txrx_synth_cp_calib : ref_clk_hz 40000000 : is_tx 1
ad9361_rfpll_set_rate: Rate 100000000 Hz Parent Rate 40000000 Hz
ad9361_fastlock_prepare: RX Profile 0: Un-Prepare
ad9361_rfpll_vco_init : vco_freq 6400000000 : ref_clk 40000000 : range 0
ad9361_rfpll_vco_init : freq 6373 MHz : index 44
ad9361_load_gt: frequency 200000000
ad9361_load_gt: frequency 200000000 (band 0)
Calibration TIMEOUT (0x247, 0x2)
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_set_rate: Rate 100000000 Hz Parent Rate 40000000 Hz
ad9361_fastlock_prepare: TX Profile 0: Un-Prepare
ad9361_rfpll_vco_init : vco_freq 6400000000 : ref_clk 40000000 : range 0
ad9361_rfpll_vco_init : freq 6373 MHz : index 44
Calibration TIMEOUT (0x287, 0x2)
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_load_mixer_gm_subtable
ad9361_gc_setup
ad9361_rx_bb_analog_filter_calib : rx_bb_bw 9000000 bbpll_freq 983040000
ad9361_run_calibration: CAL Mask 0x80
ad9361_tx_bb_analog_filter_calib : tx_bb_bw 9000000 bbpll_freq 983040000
ad9361_run_calibration: CAL Mask 0x40
ad9361_rx_tia_calib : bb_bw_Hz 9000000
ad9361_tx_bb_second_filter_calib : tx_rf_bw 18000000
ad9361_rx_adc_setup : BBBW 8606895 : ADCfreq 245760000
c3_msb 0x0 : c3_lsb 0x15 : r2346 0x1 : 
invrc_tconst_1e6 484923, sqrt_inv_rc_tconst_1e3 696
scaled_adc_clk_1e6 384000, inv_scaled_adc_clk_1e3 2604
tmp_1e3 1000, sqrt_term_1e3 619, min_sqrt_term_1e3 1000
ad9361_bb_dc_offset_calib
ad9361_run_calibration: CAL Mask 0x1
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rf_dc_offset_calib : rx_freq 200000000
ad9361_run_calibration: CAL Mask 0x2
ad9361_tx_quad_calib : bw 9000000 clkrf 30720000 clktf 30720000
Tx NCO frequency: 1920000 (BW/4: 2250000) txnco_word 1

ad9361_run_calibration: CAL Mask 0x10
ad9361_tracking_control : bbdc_track=1, rfdc_track=1, rxquad_track=1
ad9361_pp_port_setup
ad9361_set_tx_atten : attenuation 10000 mdB tx1=1 tx2=1
ad9361_rssi_setup
ad9361_txmon_setup
Device is in 5 state, moving to a
ad9361_bist_prbs: mode 2
ad9361_calculate_rf_clock_chain: requested rate 10000000 TXFIR int 1 RXFIR dec 1 mode Nominal
ad9361_calculate_rf_clock_chain: 1280000000 80000000 40000000 20000000 10000000 10000000
ad9361_calculate_rf_clock_chain: 1280000000 80000000 40000000 20000000 10000000 10000000
ad9361_set_trx_clock_chain
ad9361_bbpll_set_rate: Rate 1280000000 Hz Parent Rate 40000000 Hz
Calibration TIMEOUT (0x5E, 0x80)
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 1280000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 80000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 40000000 Hz Parent Rate 80000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rssi_setup
ad9361_auxadc_setup
ad9361_calculate_rf_clock_chain: requested rate 61440000 TXFIR int 1 RXFIR dec 1 mode Nominal
ad9361_calculate_rf_clock_chain: 983040000 491520000 245760000 122880000 61440000 61440000
ad9361_calculate_rf_clock_chain: 983040000 245760000 122880000 61440000 61440000 61440000
ad9361_set_trx_clock_chain
ad9361_bbpll_set_rate: Rate 983040000 Hz Parent Rate 40000000 Hz
Calibration TIMEOUT (0x5E, 0x80)
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 491520000 Hz Parent Rate 983040000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 245760000 Hz Parent Rate 491520000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 61440000 Hz Parent Rate 61440000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rssi_setup
ad9361_auxadc_setup
ad9361_dig_tune: Tuning RX FAILED!
ad9361_bist_prbs: mode 0
ad9361_bist_loopback: mode 1
ad9361_calculate_rf_clock_chain: requested rate 10000000 TXFIR int 1 RXFIR dec 1 mode Nominal
ad9361_calculate_rf_clock_chain: 1280000000 80000000 40000000 20000000 10000000 10000000
ad9361_calculate_rf_clock_chain: 1280000000 80000000 40000000 20000000 10000000 10000000
ad9361_set_trx_clock_chain
ad9361_bbpll_set_rate: Rate 1280000000 Hz Parent Rate 40000000 Hz
Calibration TIMEOUT (0x5E, 0x80)
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 1280000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 80000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 10000000 Hz Parent Rate 20000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rssi_setup
ad9361_auxadc_setup
ad9361_calculate_rf_clock_chain: requested rate 61440000 TXFIR int 1 RXFIR dec 1 mode Nominal
ad9361_calculate_rf_clock_chain: 983040000 491520000 245760000 122880000 61440000 61440000
ad9361_calculate_rf_clock_chain: 983040000 245760000 122880000 61440000 61440000 61440000
ad9361_set_trx_clock_chain
ad9361_bbpll_set_rate: Rate 983040000 Hz Parent Rate 40000000 Hz
Calibration TIMEOUT (0x5E, 0x80)
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 491520000 Hz Parent Rate 983040000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 245760000 Hz Parent Rate 491520000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 61440000 Hz Parent Rate 61440000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rssi_setup
ad9361_auxadc_setup
ad9361_dig_tune: Tuning TX FAILED!
ad9361_bist_loopback: mode 0
ad9361_set_trx_clock_chain
ad9361_clk_factor_set_rate: Rate 245760000 Hz Parent Rate 983040000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 122880000 Hz Parent Rate 122880000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_clk_factor_set_rate: Rate 30720000 Hz Parent Rate 61440000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
ad9361_rssi_setup
ad9361_auxadc_setup
ad9361_init : AD9361 Rev 2 successfully initialized
Initialized AD9361
ad9361_load_fir_filter_coef: TAPS 128, gain -6, dest 3
ad9361_load_fir_filter_coef: TAPS 128, gain 0, dest 131
Set up FIR filters
Initialized DAC: using DMA
Initialized ADC
Waiting For Command from Console

Outcomes