I have an application where the Clocks to the AD9102 are provided by a Gated PLL that has a variable clock rate output. The intended result being "bursts" of pulses at a nominal repetition rate. The Gated clock train produced will clock out a burst of pulses of tuned amplitudes from the AD9102.
I missed the need to have several clocks that must be provided after /Trigger goes high in Figure 42 in the data sheet. So the clocks and the desired pattern period stop simultaneously, which produces very unpredictable result. Figure 42 shows a dashed line on the clock train. My worry is that the dashing means that I need a lot more clocks to be provided that the 4 rising edges shown before the "Pattern Off" occurs. I can easily provide 4 or 8 or more but would like to know how many more I need to provide? (before making new hardware!)
There is no clear indication of how many clocks are needed.