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Clock reference frequency change tolerance (AD9951)

Question asked by Rice on Dec 12, 2014
Latest reply on Dec 19, 2014 by Rice

Hello all,

 

I am currently using an AD9951 DDS device in my design. Apart from the digital FTW0 register to modulate frequency I want it to track at the output the frequency changes seen in the input clock reference. Unfortunately I cannot see in the datasheet any information about the dynamic capabilities of the clock input.

 

I would like to know how much frequency change at the reference clock is tolerated by the PLL (clock multiplier) without unlocking. I would also like to know the same parameter in case the PLL is bypassed (that is, how much does the internal DDS circuitry allows).

 

Thank you very much in advance.

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