AnsweredAssumed Answered

adv7604 custom res 1280 x 960

Question asked by mhb27 on Dec 11, 2014
Latest reply on Dec 15, 2014 by mhb27

i followed through on the auto graphics process for non supported graphics but it seems to still not be getting a lock no matter what i change.

 

DVI input format:
Hactive:     1280

Vactive:     960

I/P:          progressive

Htotal:     1800

Hblank:     520

Hfront:     98

Hsync:     114

Hback:     308

Hpol:          low

Vtotal:     981

Vblank:     21

Vfront:     1

Vsync:     3

Vback:     17

Vpol:          low

HFreq:     58.1KHz

VFreq:     59.2Hz

Pclock:     104.6MHz

 

code:

//  Program the primary mode to graphics: PRIM_MODE[5:0] = 0b0010

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_IO, ADV7604_REG_IO_PRIM_MODE, 0b00000010 );

 

 

  //  Program the video standard to auto graphics: VID_STD[3:0] = 0b00111

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_IO, ADV7604_REG_IO_VID_STD, 0b00000111 );

 

 

  //  Generate the pixel clock for 1280 x 960 resolution

  //  Firstly, PLL_DIV_MAN_EN is set to 1 to enable manual programming of the PLL block.

  //  Secondly, one of the two following methods is used to calculate the value of PLL_DIV_RATIO[12:0] to give the required pixel clock.

  //  Method one or method two is chosen, depending on the information available about the non standard format.

  u_int32_t pc =  104600000;

  u_int32_t hsync = 58100;

  u_int32_t pClock = pc/hsync;

  u_int8_t first = (pClock>>8)| 0xC0;

  u_int8_t last = pClock;

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_IO, ADV7604_REG_IO_16, first );

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_IO, ADV7604_REG_IO_17, last );

 

 

  //  Configuring the Free Run Mode Line Length

  //  The expected line length for non standard formats must be programmed to the CP core. FR_LL[10:0] (free run line length) is the number

  //  of system clock cycles in the ideal line length of the video format.

  uint8_t baseReg;

  u_int32_t sysClock = 28636300;

  u_int32_t freemode = sysClock/hsync;

  first = freemode>>8;

  last = freemode;

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_8F, first );

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_90, last );

 

 

  status = adv7604_read( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_46_2, &baseReg );

  baseReg |=  (first& 0b111);

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_46_2, baseReg );

     status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_48, last );

 

 

  //  Setting the Free Run Mode Number of Lines per Field

  //  The expected number of lines per field for non standard formats must be programmed to the CP core.

     u_int16_t vTotal = 981;

     u_int16_t numLines = vTotal<<4;

     first = numLines>>8;

     last = numLines;

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_AB_1, first );

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_AB_2, last );

 

 

  //  Configuring the Interlaced or Progressive Parameter

  //  Progressive Mode

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_91, 0x50 );

 

 

  // Adjust the horizontal and vertical position, height, and width by varying the values of DE_H_START[9:0] and DE_H_END[9:0].

  // Also need to adjust the values in DE_V_START[9:0] and DE_V_END[9:0]

  // s sign  e sign

  // DE_H_START

  // DE_H_END

  uint16_t de_h_start = 308;

  uint16_t de_h_end = -98;

  status = adv7604_read(this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_8B, &baseReg );

  baseReg &= 0xF0;

  baseReg += (0x03&(de_h_start>>8))<<2;

  baseReg += (0x03&(de_h_end>>8));

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_8B, baseReg);

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_8C, (de_h_end & 0xff) );

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_8D, (de_h_start & 0xff) );

 

 

  // DE_V_START split DE_V_END

  uint8_t de_v_start = 17;

  uint8_t de_v_end = -1;

  baseReg = de_v_start<<4;

  baseReg += (de_v_end & 0x0F);

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_8E, baseReg );

 

 

  // CP_START_VBI

  // split

  // CP_END_VBI (no interlacing)

  uint16_t cp_start_vbi = 981-1+1;

  uint16_t cp_end_vbi = 3+17+1;

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_A5_1, (cp_start_vbi>>4) );

  baseReg = (cp_start_vbi<<4)& 0xF0;

  baseReg+= ((cp_end_vbi>>8)& 0x0F);

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_A5_2, baseReg );

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_A7, (cp_end_vbi&0xFF) );

 

 

  // CP_START_VBI_EVEN

  // split

  // CP_END_VBI_EVEN (interlacing)

  uint16_t cp_start_vbi_even = 981-0+1;

  uint16_t cp_end_vbi_even = 981+3+18+1;

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_A8_1, (cp_start_vbi_even>>4) );

  baseReg = (cp_start_vbi_even<<4)& 0xF0;

  baseReg+= ((cp_end_vbi_even>>8)& 0x0F);

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_A8_2, baseReg );

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_AA, (cp_end_vbi_even&0xFF) );

 

 

  //  Adjusting the Vertical or Horizontal Alignment

  //  Adjust the EAV and SAV code position by varying the values in CP_START_EAV[11:0] and CP_START_SAV[11:0]

  // CP_START_SAV

  // split

  // CP_START_EAV

  uint16_t cp_start_sav = 114+308-4;

  uint16_t cp_start_eav = 1800-98;

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_A2_1, (cp_start_sav>>4) );

  baseReg = (cp_start_sav<<4)& 0xF0;

  baseReg+= ((cp_start_eav>>8)& 0x0F);

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_A2_2, 0xa6 );

  status = adv7604_write( this->adv7604_fd, this->hENCFPGA, ADV7604_ADDR_CP, ADV7604_REG_CP_A4, (cp_start_eav &0xFF) );

Outcomes