Hello,

Below is a table showing SHARC performance from Analog Devices website.

When I measured the number of cycles executing Talkthru_IIR_Accelerator example packaged in VDSP5.1, I got more cycles than cycles shown above. Total cycles measured is 31248. In the example, the number of biquads is 3 and data length is 512.

31248 / 512 = 60cycles. 60 / 3 biquads = 20 cycles. That is approximately 150ns. Much larger than described in tha table.

Could you explain why?

Best Regards,

Mack

Hi Mack,

In the ADSP-21489 datasheet, the mentioned algorithm benchmarks are captured from the handwritten optimized assembly code (Core algorithm), but not for the Accelerator.

In most of these cases the core takes fewer cycles than the IIR accelerator. The difference between the cycles taken by the core and the accelerator is almost negligible for lower order IIR operations but becomes more significant for higher order IIR operations. This difference increases as the window size is increased.

Thanks & Regards

Jithul