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I2S BCLK on SSM2603

Question asked by axel_lagrange on Dec 11, 2014
Latest reply on Dec 15, 2014 by axel_lagrange



I have question about the I2S management with SSM2603. 


My goal is to use the SSM2603 ADC and to transfer the audio data to a microcontroller via the I2S bus.


In the case where the SSM2603 is master on I2S I don't understand why the BCLK is greater than sampling rate  * word length * 2 and not strictly equal

For example, with a sample rate at 16 KHz and 16 bits resolution, as the MCLK is 12.288 MHz the BCLK generated by the SSM2603 is 3,072 MHz.


But in this configuration the microcontroller (cortex-M3) seems to wait for a BCLK strictly equal at sampling rate  * word length * 2 ==> 51.2KHz