Hello, I'm trying to set the HSYNC and VSYNC polarity to active low; however, writing the PHS and PVS registers does not have any affect when viewing the signals on a oscilloscope. Do you have any recommendations.
Hello Mr. Guiffrida,
The PHS and PVS bits do work correctly on the ADV7280.
I double checked this by testing the functionality of these bits on an ADV7280 evaluation board.
Below are a few things that you should check on your system.
1) Ensure ADV7280 has been programmed correctly using an Analog Devices recommended script.
2) Ensure that the HS and VS/Field/SFL pins are being probed correctly with an oscilloscope.
3) Ensure that register 0x0E is equal to 0x00. This will ensure that you are in the correct User submap.
4) By default the VS/Field/SFL pin outputs field information. Toggling the PVS bit will have no effect in this mode. Ensure that the VS/Field/SFL pin outputs vertical sync information by setting User map, register 0x6B bits [2:0] to 0b'001. The VS/Field/SFL pin will now output vertical sync information and the PVS bit will now work.
5) By default the HS pin will output horizontal sync information (double check this by ensuring that User map, register 0x6A bits [2:0] are equal to 0b'000). The PHS bit should work.
See the ITU-R BT.656 OUTPUT CONTROL REGISTERS section of the ADV728x hardware manual for more information. http://www.analog.com/static/imported-files/user_guides/ADV7280_7281_7282_7283_UG-637.pdf
Analog Devices Inc.
Thank you for the response Rob. I've insured that the registers are set correctly. Does polarity flipping work when the deinterlacer is enabled. Because when the deinterlacer is enabled, I don't see the polarity change; however, when the deinterlacer is disabled, I see the polarity change.
Apologies you are correct. Different bits are needed to invert the synchronization pins (HS, VS, etc) when the deinterlacer (I2P core) is enabled.
The bits to invert the synchronization pins in progressive mode are contained in the VPP map. The ADI recommended scripts for the ADV7280 set the VPP device address to 0x84.
VPP Map; register 0x5B bit  is set to 1, then the horizontal synchronization (HS) output is inverted.
VPP Map; register 0x5B bit  is set to 1, then the vertical synchronization (VS) output is inverted.
VPP Map; register 0x5B bit  is set to 1, then the data enable (DE) output is inverted.
VPP Map; register 0x5B bit  is set to 1, then the filed (FLD) output is inverted.
The default value of VPP Map; register 0x5B is 0x80. Please leave VPP Map; register 0x5B bits [4:6] at the value 0b'000. VPP Map; register 0x5B bits  is used to enable/disable advanced timing mode.
I will add the documentation for VPP Map; register 0x5B bit [0:3] in the next revision to the ADV728x hardware manual.
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