I am facing a new problem with the ADV7188.
I actually copied the design of the ADV7188 from a previous design to a new design.
In the previous design the following problem doesn't appear.
What was changed is the FPGA that was connected to it in the previous design but we double checked the new FPGA pinout and it seems to be OK.
I even use the initialization program that I am using successfully in the previous design.
What I have noticed that as soon as I activate ADC0 (write 0x17 to address 0x3A)
the video signal (coming from the ADV7341) that was relatively stable turns very noisy where the main noise at 5oKhz (2-3 peaks during each line cycle). Looking at the voltage at the card (at all their levels) shows same noise, synced with the video noise on the scope, and offcourse that over the monitor the picture that was quite good turns to be very noisy as well.
Can you suggest where to look?
No need to mention there is very very urgent problem to solve ...