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SPI SLAVE mode, communication problem

Question asked by Aleksandr.Loiko on Dec 8, 2014
Latest reply on Jan 15, 2015 by jobo23

Hi, all!

 

We have problem with SPI2 slave mode on ADSP BF-707.

 

spi_slave.png

 

SPI is configured as CPOL = 0, CPHA = 0 in slave mode.

 

PROBLEM: On picture we can see, that the first byte was sent correctly (in the second transaction) but subsequent bytes are wrong (bits 7 and 6 are 0).

 

We have tried all possible modes, but had no luck.

Below is source code of SPI application.  It processes data from SPI Master that sends to BF-707 SPI FLASH command Fast Read (0xB) and Slave (BF-707) answers 0xFF. 

We have checked that everything is configured according to manual. Please, help us or brains will explode

The code of application listed below:

 

void SPIStatusHandler(uint32_t iid, int32_t index, void* cb_param)

{

    uint32_t ilat = *pREG_SPI2_ILAT;

 

    *pREG_SPI2_ILAT_CLR = ilat;


   return iid;

}

 

 

uint32_t SPIRxHandler(uint32_t iid, int32_t index, void* cb_param)

{

 

    uint8_t RxData;

 

    RxData = (uint8_t)ADI_ANOM_16000030_READ32(pREG_SPI2_RFIFO);

 

    *pREG_SPI2_TFIFO = 0xFF;

 

    return iid;

}

 

void SPI2_Init(void)

{

    /* init SPI2 pinmux */

        /* clear appropriate bits */

    *pREG_PORTB_MUX &=  ~(SPI2_CLK_PORTB_MSK_MUX | SPI2_MISO_PORTB_MSK_MUX | SPI2_MOSI_PORTB_MSK_MUX | SPI2_SS_PORTB_MSK_MUX);

    /* PORTx_MUX registers */

    *pREG_PORTB_MUX |= SPI2_CLK_PORTB_MUX | SPI2_MISO_PORTB_MUX | SPI2_MOSI_PORTB_MUX | SPI2_SS_PORTB_MUX;

 

    /* PORTx_FER registers */

    *pREG_PORTB_FER_SET = SPI2_CLK_PORTB_FER | SPI2_MISO_PORTB_FER | SPI2_MOSI_PORTB_FER | SPI2_SS_PORTB_FER;

 

    /* SPI2 initialization */

    *pREG_SPI2_CTL = ENUM_SPI_CTL_EN;

    *pREG_SPI2_CTL = ENUM_SPI_CTL_DIS; //reset RXFIFO, TXFIFO

    *pREG_SPI2_STAT = 0xFFFFFFFF;

 

    *pREG_SPI2_CTL = ENUM_SPI_CTL_MISO_EN | ENUM_SPI_CTL_HW_SSEL | ENUM_SPI_CTL_SLAVE;

 

    *pREG_SPI2_IMSK_SET = ENUM_SPI_STAT_TC_HI | ENUM_SPI_STAT_ROR_HI;

 

    *pREG_SPI2_RXCTL = ENUM_SPI_RXCTL_RDR_NE | ENUM_SPI_RXCTL_RX_EN;

 

    *pREG_SPI2_TXCTL = ENUM_SPI_TXCTL_ZERO | ENUM_SPI_TXCTL_TX_EN;

 

    int32_t index = adi_rtl_register_dispatched_handler (ADI_RTL_SEC_IID(45),

SPIStatusHandler, NULL);

 

    adi_sec_EnableSource(45, true);

    adi_sec_EnableInterrupt(45, true);

    adi_osal_ActivateHandler(ADI_RTL_SEC_IID(45));

 

    index = adi_rtl_register_dispatched_handler (ADI_RTL_SEC_IID(46),

SPITxHandler, NULL);

 

    adi_sec_EnableSource(46);

    adi_sec_EnableInterrupt(46, true);

    adi_osal_ActivateHandler(ADI_RTL_SEC_IID(46));

 

    index = adi_rtl_register_dispatched_handler (ADI_RTL_SEC_IID(47),

  SPIRxHandler, NULL);

 

    adi_sec_EnableSource(47, true);

    adi_sec_EnableInterrupt(47, true);

    adi_osal_ActivateHandler(ADI_RTL_SEC_IID(47));

 

  *pREG_SPI2_CTL |= ENUM_SPI_CTL_EN;

}

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