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AD9364 FB_CLK pin connection in LVDS mode

Question asked by Raveendra on Dec 7, 2014
Latest reply on Dec 8, 2014 by tlili

Hi All,

 

 

I designed a custom board by using AD9364 and XC7A100(Artix-7) FPGA. In this board i followed the design same as AD-FMCOMMS2 like connected chip by using LVDS mode, connected data interface to 2.5 V Bank of Artix-7 FPGA.

But unfortunately i conncted FB_CLK_P pin to IO_L13N pin of FPGA instead of IO_L13P pin of FPGA. That means Positive and negative swapped when connecting to FPGA. Will it lead to any prroblem while collecting or sending data to/from AD9364

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