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HMC767 unstable, loop filter design?

Question asked by roadrunner Employee on Dec 3, 2014
Latest reply on Jul 13, 2015 by MRichardson

 

I purchased the HMC767 eval kit which is designed for a 50 MHz reference.  My system

uses a 10 MHz reference, so I used the Hittite PLL design software to

design a new loop filter.  I kept the same architecture as the eval
board (activeC with 4 sections), so I'm just swapped component values.

The screen capture of the new design is attached.  I used the same

size and type of components that the eval board used:  R2, R3, R4 are

0402, 1%;  C1 and C2 are 0603, X7R; C3 is 0603, C0G; C4 is 0402, X7R.

 

The synthesizer is very unstable with this design.  It does

occasionally lock, but not for long.

  

My questions are:

 

1)  Do you have suggestions for a better loop filter design for 10

MHz.  Note, this is just a fixed 9.25 GHz source, no tuning required.

I can compromise on phase noise if necessary.

 

2)  The unmodified eval board always drew 8 mA from the +15 V supply.

I current limit that supply at 20 mA, but when the new board goes

unstable the current will bounce around up to the current limit.  What

should I current limit that supply to?  Would 20 mA damage the device?

  Should I raise the current limit?

 

3)  Are there any software settings that might help with this?  I

tried the HiK option but that did not change anything.

 

4)  Do you have a suggestion for the max ratio between loop BW and

comparison frequency?  I'm used to keeping that ratio <100, but the

original eval board had a ratio of 380.  The new filter has a ratio of

250.  Would widening the loop bandwidth help?

 

5)  Any other suggestions or tips are appreciated.

 

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