AnsweredAssumed Answered

ADAU1761 Problems: PLL and Alias

Question asked by reg-audio on Dec 2, 2014
Latest reply on Dec 4, 2014 by DaveThib

Hello @everyone,

 

I'm currently using the ADAU1761 in combination with the zedboard.

The following Problems occured: There seems to be no way of configuring the PLL without it producing Jitter.

To be exact, I tried providing 10MHz to MCLK. Setting R=4, N=572 and M=625 should result in a PLLoutput frequency of 49,152MHz.

In Combination with the INFREQ prescaler set to 1024 I reach a sampling frequency of 48kHz.

Now, when inserting 1kHz to the Line-In, I receive a symmetrical spectrum with 937,5Hz, 968,75, 1000Hz, 1031,25 and 1062,5(also see attachment), which leads me to the conclusion, that the PLL causes jitter, which intermodulates with my test signal.

The same configuration delivers a clean signal when the PLL is disabled (MCLK=12,5MHz, INFREQ=256 -> fs=48828,125Hz).

Are there any known problems to the PLL especially in combination with the zedboard?

 

Furthermore, there are alias-effects when I try to use sampling frequencies other than 48 (or 48,828)kHz.

For example I tried MCLK=50MHz, prescaler 512 oder MCLK=25MHz, prescaler 256 and so on...

My first thought was, that the digital filters (dicimation and interpolation) might be the problem.

Any hints for that problem?

 

Greetings,

Philipp

 

P.S.: Just to make sure, I added the missing capacitors C23 and C24. Those are marked as 100nF in the schematic but weren't equiped on the board. After a short simulation, I decided to fit 1nF, which leads to a corner frequency of about 100kHz.

Attachments

Outcomes