I understand from the datasheet that the ADV7511 does only support 32Bit and 64Bit mode for the in I2S interface.
The 64 Bit would require an SCLK of 3.072MHz if the audio sample rate is set to 48KHz.
I just want ot make sure that we don't miss here anything.
Our current design with other peripheral chips uses an SCLK of 12.288MHz and a 256Bit I2S mode with many time multiplexed audio channels. It would be very convenient for us to use the existing 12.288MHz SCLK clock also for the ADV7511.
Can you please let me know if it is possible to configure the ADV7511 in a way that it supports 12.288MHz SCLK with 48KHz audio sample clock for the I2S interface.