My question pertains to connecting the clocks on a daisy-chained pair of AD1974 ADCs.
My design uses 2 pairs of daisy-chained ADCs to create two TDM8 bitstreams to go into two of the I2S inputs on the ADAU1452 dsp.
I'm using a single 12.288MHz crystal on the dsp, and I'm picking off the XTALOUT pin to go into an 8-ouput clock buffer. Each 1974 ADC (and a 1966 DAC) gets it's own clock buffer line to drive its MCLKIN pin. (Any advantage to feeding the external clock buffer from CLKOUT of dsp?)
I configure the first ADC as master, and connect its LRCLK/BCLK lines to the matching input clock domain on the dsp.
So on the 2nd ADC is it better to slave it from the MCLKOUT of the master ADC, or is it OK to slave it from one of the buffered clock lines?
In either case, what's the best source for the BCLK/LRCK inputs on the slave ADC? Is it OK to drive the dsp clock domains AND the slave ADC from the master ADC's BCLK/LRCLK?
Thanks for any advice you can offer.