I am working on a prototype demonstration on the AD 9364 based FMCOMMS4 board with ZC-706. I am using the reference design hdl-hdl_2014_r1 and its corresponding no-os software. For the prototype demonstration, I need to place a piece FPGA hardware after the util_dac_unpack block that does some operation on the DAC input. This seems to be working fine. I would like to capture the output of this processing using the DMA design as used to capture the ADC samples. That is use an util_adc_pack block followed by a axI_dmac block configured for writing to memory (just like how the ADC AXI DMA is configured).
While the above design works but I am seeing that every alternate samples is lost. I am using the dac_valid input to util_dac_unpack as the valid for cloned util_adc_pack block.
Can you please help me with debugging this problem? If required, I can send additional information such as snapshot of the design, etc.