A customer of mine is seeking to reduce the number of JESD204B lanes in which he needs to interface his FPGA to the AD9625.
The reason is due to the pricing of the FPGA. If he can interface to the AD9625-1.5 using 4 lanes, then he can save a fortune on the FPGA.
According to Table 14 in the data sheet, this is possible by selecting "fs x 4" mode. In this mode L=4 and F=2.
In doing this though, what is the customer sacrificing in using this mode?