I have already studied the datasheet (Rev. A) quite a time, but I can't solve a few questions by myself:
1. What is the 'Trigger to Output Delay' (p.8)? Especially when considering Fig. 43?
2. What does 'Continuous waveforms ignore pattern periods.' (p.25) exactly mean? Focus lies on 'period'. This also leads me to my third question:
3. WAVE_SELx offers two unmodulated prestored waveform modes, with and without 'START_DELAYx and PATTERN_PERIOD'. The difference is clear to me, but I couldn't find out when the waveforms stop in those two cases. Probably at the end of the pattern period ?
4. How long is the phase offset word? The descriptions for DDSx_PHASE don't mention a restriction, although 16 bit long, but in a sidenote in the description of the PHASE_MEM_EN3 bit, it says 8 bit. Is this right, (and if yes, why not more????)? If so, please make this more visible in future revisions of the datasheet.
5. On p.27 it says 'Each of the SRAM address counters can be programmed to be incremented by CLKP/CLKN (default) or by the rising edge of the DDSx MSB.'. The rising edge of a byte? Could you please explain this to me?
Sorry for all those questions, but they are quite relevant to my design considerations. Thanks in advance,