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ADV7391 in four bar test shows a fuzzy image

Question asked by ray.sun Employee on Nov 26, 2014
Latest reply on Dec 9, 2014 by GuenterL



Here is the output wave issue about ADV7391. Customer did a comparison test between ADV7179 and ADV7391 with standard four bar pattern.


  1. Signal chain: FPGAà Ycrcb 8bit SD PAL signal à ADV7391à4M cable à OSC(check the wave) or monitor (check the image)








Please see the four bar is vague on the screen and from the OSC, its slew rate is slower than ADV7179 and the negative peak cannot reach the 0V, however, ADV7179 could. I believe this is the reason of breezing of this picture.


I have checked the attachment schematics and think it is same to our recommended one. Especially the Rset, output R load. Would you please check it again?


Below is the setting of registers. I personal think if the image could be sent out, there is low risk of wrong setup. Please also help check it.


1  7391 current register setting(PAL)

    uint8 address7391[12] =


        0x17, // 00 MR0 MODE REGISTER 0

        0x00, // 01 MR1 MODE REGISTER 1

        0x01, // 02 MR2 MODE REGISTER 2

        0x80, // 03 MR3 MODE REGISTER 3

        0x82, // 04 MR4 MODE REGISTER 4

        0x84, //test 0x84

        0x88, //test 0x88


        0x8c, // 05 reserved

        0x8d, // 06 reserved

0x8e, // 07 TR0     TIMING REGISTER 0

0x8f // 08 TR1     TIMING REGISTER 1



    uint8 data7391[12] =


        0x02, // 00 MR0 MODE REGISTER 0

        0x1e, // 01 MR1     MODE REGISTER 1 1c

        0x00, // 02 MR2 MODE REGISTER 2

        0x11, // 03 MR3 MODE REGISTER 3  11

        0x53, //d3

        0x00, //test 0x00   color bar 40

        0x00, //test 0x00


        0x0c, // 05 reserved

        0x8c, // 06 reserved

        0x79, // 07 TR0 TIMING REGISTER 0

        0x26 // 08 TR1 TIMING REGISTER 1


See schematics as below:

2014-11-26 14 43 01.jpg