AnsweredAssumed Answered

How to minimize lock time of ADF4153

Question asked by kt315 on Nov 24, 2014
Latest reply on Dec 8, 2014 by Brigid.Duggan

Dear friends

 

I need to obtain the lock time of PLL ADF4153 strictly less than 1 ms. The reference frequency is 12.8 MHz, PFD frequency is 6.4 MHz, loop bandwidth is 7.5 kHz. RFout = 320 MHz (this is slightly less than minimum RFout from datasheet). In attachement - my project from ADIsimPLL.

Unfortunately I cannot stabilize the PLL lock time. It appears to be random (from 600 ms to 2000 ms) after writing registers.

 

Here is the sequence I write into registers (from datasheet, page 18 "INITIALIZATION SEQUENCE"):

000003

0003C7

0003C6

108401

0C8004

0003C2

 

Figure 1 - Waveforms from oscilloscope (two different curves resulting from the same initialization sequences with the same external conditions. It is seen that the lock time strongly varies)

image_oscilloscope.png

 

Probably the internal state of ADF4153 may cause lock time to randomize when LE goes high after procedure of writing registers.

Wouldn't you advise me what should I do to stabilize and minimize the lock time as much as possible?

 

Thanks in advance

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