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bug in dest_fifo_inf.v (axi_dmac)

Question asked by njp on Nov 24, 2014
Latest reply on Feb 26, 2015 by njp

I believe I've found a bug in dest_fifo_inf.v.  I found it with Chipscope.


Note though that I believe this bug only comes about when trying to read from the FIFO with a continuously high read enable.


Because the signals "data_ready", "underflow", and "valid" are connected to an AXI interface, these lead to an extra valid (for example, when trying to read 5 continuous data words, you get 6 where the 6th is garbage data). An easy fix to this is to make these signals combinatorial.


You can mask this bug by only having a valid every other clock cycle, which the util_dac_unpack does I believe.