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On DAQ2 ZC706 reference design, why is the JESD204b not direcly connected to the JESD204B XIlinx IP core?

Question asked by clofquist on Nov 21, 2014
Latest reply on Nov 28, 2014 by CsomI

A. Does the axi_jesd_gt.v provide data alignment (channel/lane alignment)?

B. Is this the way to pull out the eye-scan data and other debug information?

C. Has the JESD204B Xilinx core changed from Vivado 2013.4 (ther release you recommend) to 2014.3.1 that will provide design challenges – anything you know of?