first of all : excellent forum, nearly all of my questions solved by reading some posts. Good search function.
Now the situation and question:
In our design we need a receiver LO frequency around 1100 MHz. Phase noise requirements are nearly not existent, also no exorbitant fine channel spacings.
The same system also contains a very high power oscillator which transmits pulse trains from time to time on a similar frequency. Power is so high that shielding can not physically avoid leakage of some TX power into the housing of the system, hitting the receiver PCB.
As a further requirement, the receiver must gain full sensitivity within a few microseconds after the last TX pulse has been sent. Thus, the PLL must be stable and not being influenced by injection pulling or the like.
In the past, we successfully used a discrete 0,5"square VCO and a PLL from NatSemi, which has become obsolete, but performed excellent for lots of years.
In a redesign trial, we switched to the similar Fujitsu PLL MB15Exx series, which shows big problems with this. The RX PLL unlocks for many hundred microseconds on each TX pulse. This causes trouble, and can only be avoided by huge shielding redesign etc. => not good
But luckily there are fine parts from ADI :-)
We've come to the conclusion that an Integrated PLL/VCO as the ADF4360-6 would be the best choice for this application, as the path between PLL and VCO is internal to the chip and maybe not very susceptible to any PCB trace antenna RF pickup effects we had experienced in the Fujitsu trial system.
Before trying everything out in a prototype, the key questions:
Might it be even better to use the ADF4360-1 on 2200MHz and the divide-by-2 feature (plus added lowpass filter against squarewave harmonics) instead of the -6 version (without division) ?
If we'll get issues with injection pulling on the -6 version, might doubling the PLL frequency help a lot, or not at all ?
best regards and many thanks in advance