I am considering the use of the ADP1712 (+3.3V output) to power the ADIS1620x devices in a reference design. The ADIS1620x works best when its start-up waveform resembles a linear ramp that moves from 0 to 3V in <100us. Using the math on page 10 of the ADP1712 datasheet, it appears like using a 150pF capacitor on the SS pin will support this type of ramp rate, but I am wondering how this will respond to a slowly increasing Vin. It looks like the UVLO function will only provide protection for Vin < 2V.
This leads to a few questions, which we would appreciate help with if possible:
- do you have a simple reference circuit for managing the Enable pin, so that they device will not start until Vin is sufficiently high to support the desired ramp on the ADP1712's output?
- Does the enable pin get pulled low like the SS pin when the device is not functioning?
- With this, would connecting the Enable pin to VDD through a resistor, while having a capacitor on the Enable pin work?