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AD9129 Questions

Question asked by roadrunner Employee on Nov 18, 2014
Latest reply on Nov 18, 2014 by danf

The
DAC has been working pretty well for us now.
A data sheet tip would be to insert a line in the register configuration
that says when to reset the FPGA PLLs.
You want to do it after the input PLL is configured, and before the data
bus DLL is configured.

 

  We have a new issue/observation…Our
receiver has a BER (bit error rate) of zero, with a signal generated by the
DAC, when we run the DAC with an output power between about -1  and -6 dBFS.

 

As we go lower than -6 dBFS, our receiver generates bit errors.  It is a function of the DAC.  I can set the DAC to -3 dBFS, and use
external attenuators to reduce the power level, and the receiver will remain
error free.
This issue seems to also be a function of data rate, at least in some cases.

The scenario I have been using the most is as follows:

 

  • 2.4576
    MHZ sampling rate
  • 900
    MHz carrier frequency
  • QPSK
  • 150
    MSps

 

So the main lobe spectrum is 750 MHz to 1050 MHz. I have the FIR40 enabled.  If
I bring the symbol rate down to about 105 MSps, the issue goes away, or if I
keep the power between -1 dBFS and -6 dBFS.
Looking
at Figure 140 in the data sheet, I estimate that the -0.5 dB point is at 0.45%
of the frequency, or 1.11 GHz.
I can turn the clock up to 2.70336 GHz, which is slightly out of range of the
AD5917-1 that I am driving the DAC with.
However, the operational range has now shifted.

 

 

The system will run error free up to 150 MSps, if the power is between -1 and -12
dBFS (so the power range expanded a bit).

 

I haven’t been able to nail down a “smoking gun”, of 2 obviously different spec A
pictures, at the 2 power levels, to give better insight into what is going
wrong. 
I have put a multiplier right at the serdes input to scale the amplitude, to
verify that I don’t have a truncation issue upstream.
  So
I should have just enough BW.  But even if I didn’t, that doesn’t explain why it is power dependent.

 

I’ve assumed that the DAC expects 2’s complement signed values on it’s input.  I can’t find a reference to this in the data
sheet.  Is this a correct assumption?
  Any other ideas as to what could be wrong?

 

As a second question, the DAC doesn’t look to be sinc compensated.  Is that correct?  I copied the filter listed in the AD9779 data
sheet and added it to my FPGA.  Does this seem reasonable?  It looks good on the
spectrum analyzer, the side lobes look to have the same peak now.

Thanks

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