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AC701/FCOMMS3 axi_ad9361 ip mods for custom no-os implementation

Question asked by labianco on Nov 17, 2014
Latest reply on Nov 6, 2015 by CsomI



Its gonna take a minute to explain my thoughts and situation before I can propose my question:


I am really trying to use the no-os microblaze core to setup the AD9361 and use VHDL to handle the baseband processor tx/rx data stuff.  I need to do this because the no-os drivers buffer the receive data and my BBP (implemented in VHDL) needs new data every clock cycle, in other words the receiver must look like an ADC to the BBP).


I first tried to remove the rx and tx signals (clk, data, frame) from the axi_ad9361 ip core in the ip integrator, but the no-os code errors out. So I tried to clean up the software to account for the missing functionality, but I got to a point where it seemed like the software was trying to use the received signal to help tune the RF front end of the AD9361 (maybe in the ad9361_dig_tune() function in ad9361.c, please correct me on this)?  This discovery/road block led me to think...maybe I can disconnect only the tx outputs from the axi_ad9361 and leave the rx inputs connected.  So, I tried this while implementing a very simple receiver in the VHDL to process the receive data. My VHDL receiver obviously needed to send the rx_clk signals into an IBUFDS so it could use the clock...vivado didn't like this because there is apparently one instantiated in the axi_ad9361 ip core...


So my general question is...what is the path of least resistance to separate the SPI configuration of the AD9361 and the baseband processor functions? And I understand that I can transfer data between the microblaze and VHDL via memory, but my already developed BBP cannot handle data wants the RF front end to look like an ADC and not a FIFO.


If the no-os code does need the rx data to tune the front end as mentioned previously (again, please correct me on this), is there a way that I can modify the axi_ad9361 core to convert the differential inputs into single ended and send it the already buffered clock (it would already be buffered in the VHDL)?


I am very open to suggestions as my only criteria is that I have to get the data to my VHDL BBP on a clock cycle basis and the BBP must never have to wait for any data buffering (it must always be available).


Thank you so much in advance,