I'm trying to connect the AD9381 to a stereo DAC (CS4353) through I2S.
I can see SCLK, MCLK, LRCLK and SDATA, all in sync and fulfill I2S demands.
The problem is that the CS4353 requires for e.g. Fs=48kHz, SCLK=128*Fs and MCLK=256*Fs, but the AD9381 gives me 64*Fs and 128*Fs, respectively.
I'm trying to configure the analog PLL (reg 0x58) so that it will satisfy my requirements, but that also scales my Fs, which is not desired. Scaling is also in non-standard rates, e.g. 73kHz.
What's the correct way to adjust MCLK w/o scaling Fs?