I am designing a board with two TS 201s, processor ID values are 0(DSP0)and 1(DSP1), the DSPs are interconnected using the cluster-bus.The width of cluster-bus is set to 64-bits,and the pipeline depth for write transactions is always one cycle. My trouble is:
When one DSP write to another DSP' s memory space through cluster-bus, a error will occur sometimes ,such as DSP1（ID=1） writes to the memory of address 0x100c0000 with the value of 0xaaaaaaaa, but actuality the vale i read from the memory of address 0x000c0000 of DSP0(ID=0) is 0x2aaaabaa, or other values, that means some bits of the value are not writen correctly .And the bits written error are not fixed, that may be through bit 0 to bit 31. I have captured the waveform of write transactions using the oscilloscope, and find that the timing of the signals always meet the requirements of datasheet including the setup time, hold time, etc. I want to make sure that is because the memory space i accessed through cluster-bus is write-protected or because of other reasons.
All the operation is in emulator mode through HPUSB , the IDE is visualdsp++ 5.0 and all the code of DSPs is executed in debugger state using the command of "step over".