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ADuC7023 Flash/Ram run problem

Question asked by roadrunner Employee on Nov 14, 2014
Latest reply on Nov 17, 2014 by EckartH

 

We are using the AduC7023 device in a power amplifier controller. When we run the code from Flash, everything works fine. All of the code is written in ARM/Thumb Assembly. When we download some of the ISR code to RAM at 0x10100, we experience a problem. After some analysis using the uVision simulator (version 4.74), I discovered that the following instruction is the culprit:

 

LDR                        R12,=RAM_Reference+RampBufferStart_OFFSET

 

RAM_Reference starts at 0x10000 and RampBufferStart_OFFSET is 0x800. We use memory from 0x11000 – 0x1103F for vectors and 0x11040 – 0x110FF for our stack.


The Assembler produces the following code for the above statement:

 

LDR     R12,[PC,#0x0080]


which doesn’t make sense because the PC for this code resides at 0x10F48. However, if I add 4 NOPs ANYWHERE in the area that gets copied to RAM, it magically works. I can add any additional multiple of 8 NOPs (32 bytes) to the 4 NOPs and it still works. If I add 4 NOPs, the PC for the code resides at 0x10F4C but adding 0x0080 to this doesn’t come anywhere near where it should be which is 0x11800. BUT(!), when executed in the simulator with the 4 NOPs, the address of 0x11800 is magically put into R12 and it works on the platform hardware as well. I don’t get it. I have tried different ALIGN commands to no avail. If someone can enlighten me as to what causes this, I would greatly appreciate it.

Thanks!

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