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ADV202 HIPI decode mode lost last four byte

Question asked by cquxxey on Nov 11, 2014
Latest reply on Nov 14, 2014 by DaveD

Hello everyone,

there's a problem when i use the adv202 in HIPI mode.The MCLK is 27Mhz.

The HIPI encode mode worked correctly,while the HIPI decode mode always lost the last four byte of the pixel data.

I use ADV202 to compress the 128*100 single component picture, and i worked correctly in HIPI encode mode.However, in decode mode, the pixel data come out from PIXEL FIFO(DMA channel 0) always lost the last four byte.

ps: The picture ,pixel data , compressed stream and decoded pixel data are in the attachment below.

   ENCODE initializition:

1. Write 0x00000008 to the PLL_HI register, 0x00000004 to the PLL_LO register

2. Wait for 1ms

3. Write 0x0000008A to the BOOT register

4. Write 0x0000000A to BUSMODE

5. Write 0x0000000A to MMODE

6. Write 0x00050000 to IADDR

7. Load <encode_2_13_0.sea>

8. Write 0x0000008D to the BOOT register

9. Write 0x0000000A to BUSMODE

10.Write 0x0000000A to MMODE

(2) Pre-initialization Routine for ADV202

1. Write 0x00057F00 to IADDR

2. Write 0x04000503 to IDATA

3. Write 0x01010000 to IDATA          //lossless

4. Write 0x00000000to IDATA      

   Write 0x00000002 to IDATA

5. Write 0xFFFF0400 to IADDR (0xb); select PMODE register

   Write 0x00140000 to IDATA (0xc); 8-bit single component

   Write 0xFFFF040C to IADDR (0xb); XTOT

   Write 0x00800000 to IDATA (0xc); 128

   Write 0xFFFF0410 to IADDR (0xb); YTOT

   Write 0x00640000 to IDATA (0xc); 100

   Write 0xFFFF044C to IADDR (0xb); VMODE

   Write 0x00120000 to IDATA (0xc), Host mode enabled for HIPI encode mode

(3) Initialization Routine for ADV202

1. Write to 0x0400 to EIRQIE

2. Wait for IRQ to be asserted

3. Read SWFLAG to ensure the program has correctly initialized (i had read the data->0xFF82)

(4) configure DMA channel 0 for pixel input

1. Write 0xFFFF1408 to IADDR

2. Write 0x00100000 to IDATA

3. Write 0xFFFF1408 to IADDR

4. Write 0x00110000 to IDATA

(5) configure DMA channel 1 for compressed data output

1. Write 0xFFFF140C to IADDR

2. Write 0x00120000 to IDATA

3. Write 0xFFFF140C to IADDR

4. Write 0x00130000 to IDATA

(6) Start program for ADV202

Write 0x0400 to EIRQFLG on the ADV202 to clear the software interrupt [SWIRQ0] and start the program

DECODE initializition

1. Write 0x00000008 to the PLL_HI register, 0x00000004 to the PLL_LO register

2. Wait for 1ms

3. Write 0x0000008A to the BOOT register

4. Write 0x0000000A to BUSMODE

5. Write 0x0000000A to MMODE

6. Write 0x00050000 to IADDR

7. Load <decode_2_16_1.sea>

8. Write 0x0000008D to the BOOT register

9. Write 0x0000000A to BUSMODE

10.Write 0x0000000A to MMODE

(2) Pre-initialization Routine for ADV202

1. Write 0x00057F00 to IADDR

2. Write 0x04000003 to IDATA

3. Write 0x00000000 to IDATA        

4. Write 0x00000002to IDATA      

   Write 0x00000000 to IDATA

5. Write 0xFFFF0400 to IADDR (0xb); select PMODE register

   Write 0x00140000 to IDATA (0xc); 8-bit single component

   Write 0xFFFF040C to IADDR (0xb); XTOT

   Write 0x00800000 to IDATA (0xc); 128

   Write 0xFFFF0410 to IADDR (0xb); YTOT

   Write 0x00640000 to IDATA (0xc); 100

   Write 0xFFFF044C to IADDR (0xb); VMODE

   Write 0x00100000 to IDATA (0xc), Host mode disabled for HIPI decode mode

(3) Initialization Routine for ADV202

1. Write to 0x0400 to EIRQIE

2. Wait for IRQ to be asserted

3. Read SWFLAG to ensure the program has correctly initialized (i had read the data->0xFF82)

(4) configure DMA channel 0 for compressed data in

1. Write 0xFFFF1408 to IADDR

2. Write 0x00120000 to IDATA

3. Write 0xFFFF1408 to IADDR

4. Write 0x00130000 to IDATA

(5) configure DMA channel 1 for pixel data output

1. Write 0xFFFF140C to IADDR

2. Write 0x00100000 to IDATA

3. Write 0xFFFF140C to IADDR

4. Write 0x00110000 to IDATA

(6) Start program for ADV202

Write 0x0400 to EIRQFLG on the ADV202 to clear the software interrupt [SWIRQ0] and start the program

Outcomes