We have a design with adv7842 where we had to adjust the phase of the LLC clock to adapt to the back-end fpga.
Ie.enabled LLC_DLL_MUX and LLC_DLL_EN and setting phase in LLC_DLL_PHASE.
This works and we can adjust the phase.
However, looking more closely at this we have found that phase-shift seems to depend on the LLC frequency.
Our LLC frequency range form 25MHz to 154MHz.
We would expect that the phase shift was constant with regards to the data/sync.
There have been some posts on this before, for instance:
But could you shed some light over phase-shift versus frequency on the LLC_DLL mux ?