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ADE7373A SPI questions

Question asked by frankd on Nov 6, 2014
Latest reply on Nov 17, 2014 by hmani



It is my understanding that if we are to maximize our use of the SPI Mode, we need to setup "DREADY" so we can get an interrupt when the DSP data has finished being updated (via an IRQ output).  But, to reset DREADY (for the next acquisition cycle) we must incur an SPI write of 7 bytes, which at 2.5MHz takes so long that we don't have time left to read much from the "working registers".  Do you know a way of setting the chip up so we can reset DREADY in the shortest time possible?

Thank you,