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ad9364 TX VCO lock bit

Question asked by mince on Nov 6, 2014
Latest reply on Nov 7, 2014 by mince

Hi,

 

I calibrated the TX LO of AD9364 for more than 8 frequencies. I saved the calibration results on the baseband processor. The difference between the minimum and maximum frequency that I have calibrated and locked at startup is about ~ 250 MHz.

 

I am loading the calibrated values into the TX fast lock profiles. Then, I am selecting the current operating frequency from TX fast lock profile table by selecting the index. The RF output of AD9364 is set to desired frequency after this operation.

 

However, I could not observe the falling of TX lock signal at control outputs even if I change the LO frequency more than 200 MHz when using fast lock profiles.

 

If the LO frequency is changed directly by baseband processor, I am observing the falling of TX lock signal at the control output bit7.  (Register 0x035 = 0x01 and Register 0x36 = 0xFF).

 

Could you help me in order to understand this situation ?

Why the RFPLL is not enter un-locked mode ?

 

In addition to, is there any method of measuring the frequency hopping time of AD9364 when using fast lock method ?

 

Best Regards,

Mustafa iNCE

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