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AD9361 sample rate in reference design

Question asked by Bhaskar on Nov 6, 2014
Latest reply on Jan 27, 2015 by DragosB

Hi

 

I am Bhaskar . I will be using ad9361 as a part of my sdr project . I am using zynq zc702 , hence I am going through the reference design and I have a few questions.

 

1.) As I understood till now , the filter configuration are set in the software are passed to the ad9361 board via SPI  . The I and Q samples for a sine wave  are generated within  the software and passed to HDL core for ad9361 via dmac transfer for bit rearrangement(as the DAC on ad9361 is of 12 bit resolution). My question is  where are we controlling the sample rate ? . In the AD9361_InitParam default_init_param we give the reference_clk_rate as 40 mega but we don't seem to use it anywhere. Please help me to understand about controlling sample rate as this will be the prime parameter in my case .

 

2.) There is a function ad9361_set_trx_path_clks in ad9361_api.h but we dont seem to use that either in the sample design , so how do we actually setting the rate of data transmission in the sample design?

 

3.) In my case I have developed a QPSK modem peripheral whose samples I want to up convert to a specific center frequency . In this how to communicate mu samples to DMAC rather then sending the pre generated sample as in reference design.

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