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AD9361-AC701-FMCOMMS2 timing constraints failure

Question asked by labianco on Nov 5, 2014
Latest reply on Nov 5, 2014 by labianco

All,

 

I have built the reference design for the AC701 project and synthesized/implemented and everything seemed to be fine.  I then added a VHDL wrapper for the top level Verilog file system_top.v.  After re-synthesizing/re-implementing everything worked except I had a timing constraint failure for the rx_clk net.  Does anyone know why this may be?

 

Thanks,

Nick

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AMU_Top is
    Port (
        sys_rst : in STD_LOGIC;
        sys_clk_p : in STD_LOGIC;
        sys_clk_n : in STD_LOGIC;
        uart_sin : in STD_LOGIC;
        uart_sout : out STD_LOGIC;
        ddr3_addr : out STD_LOGIC_VECTOR(13 downto 0);
        ddr3_ba : out STD_LOGIC_VECTOR(2 downto 0);
        ddr3_cas_n : out STD_LOGIC;
        ddr3_ck_n : out STD_LOGIC_VECTOR(0 downto 0);
        ddr3_ck_p : out STD_LOGIC_VECTOR(0 downto 0);
        ddr3_cke : out STD_LOGIC_VECTOR(0 downto 0);
        ddr3_cs_n : out STD_LOGIC_VECTOR(0 downto 0);
        ddr3_dm : out STD_LOGIC_VECTOR(7 downto 0);
        ddr3_dq : inout STD_LOGIC_VECTOR(63 downto 0);
        ddr3_dqs_n : inout STD_LOGIC_VECTOR(7 downto 0);
        ddr3_dqs_p : inout STD_LOGIC_VECTOR(7 downto 0);
        ddr3_odt : out STD_LOGIC_VECTOR(0 downto 0);
        ddr3_ras_n : out STD_LOGIC;
        ddr3_reset_n : out STD_LOGIC;
        ddr3_we_n : out STD_LOGIC;                       
        phy_reset_n : out STD_LOGIC; 
        phy_mdc : out STD_LOGIC; 
        phy_mdio : inout STD_LOGIC; 
        phy_tx_clk : out STD_LOGIC; 
        phy_tx_ctrl : out STD_LOGIC; 
        phy_tx_data : out STD_LOGIC_VECTOR(3 downto 0); 
        phy_rx_clk : in STD_LOGIC; 
        phy_rx_ctrl : in STD_LOGIC; 
        phy_rx_data : in STD_LOGIC_VECTOR(3 downto 0);    
        fan_pwm : out STD_LOGIC;
        gpio_lcd : inout STD_LOGIC_VECTOR(6 downto 0);
        gpio_led : inout STD_LOGIC_VECTOR(3 downto 0);
        gpio_sw : inout STD_LOGIC_VECTOR(8 downto 0);
        iic_rstn : out STD_LOGIC;
        iic_scl : in STD_LOGIC;
        iic_sda : in STD_LOGIC;        
        hdmi_out_clk : out STD_LOGIC;
        hdmi_hsync : out STD_LOGIC;
        hdmi_vsync : out STD_LOGIC;
        hdmi_data_e : out STD_LOGIC;
        hdmi_data : out STD_LOGIC_VECTOR(23 downto 0);      
        spdif : out STD_LOGIC;  
        rx_clk_in_p : in STD_LOGIC;
        rx_clk_in_n : in STD_LOGIC;
        rx_frame_in_p : in STD_LOGIC;
        rx_frame_in_n : in STD_LOGIC;
        rx_data_in_p : in STD_LOGIC_VECTOR(5 downto 0);
        rx_data_in_n : in STD_LOGIC_VECTOR(5 downto 0);        
        tx_clk_out_p : out STD_LOGIC;
        tx_clk_out_n : out STD_LOGIC;
        tx_frame_out_p : out STD_LOGIC;
        tx_frame_out_n : out STD_LOGIC;
        tx_data_out_p : out STD_LOGIC_VECTOR(5 downto 0);
        tx_data_out_n : out STD_LOGIC_VECTOR(5 downto 0);
        gpio_txnrx : inout STD_LOGIC;
        gpio_enable : inout STD_LOGIC;
        gpio_resetb : inout STD_LOGIC;
        gpio_sync : inout STD_LOGIC;
        gpio_en_agc : inout STD_LOGIC;
        gpio_ctl : inout STD_LOGIC_VECTOR(3 downto 0);
        gpio_status : inout STD_LOGIC_VECTOR(7 downto 0);
        spi_csn : out STD_LOGIC;
        spi_clk : out STD_LOGIC;
        spi_mosi : out STD_LOGIC;
        spi_miso : in STD_LOGIC
    );
end AMU_Top;
architecture Behavioral of AMU_Top is
 
    COMPONENT system_top PORT (    
        sys_rst : in STD_LOGIC;
        sys_clk_p : in STD_LOGIC;
        sys_clk_n : in STD_LOGIC;
        uart_sin : in STD_LOGIC;
        uart_sout : out STD_LOGIC;
        ddr3_addr : out STD_LOGIC_VECTOR(13 downto 0);
        ddr3_ba : out STD_LOGIC_VECTOR(2 downto 0);
        ddr3_cas_n : out STD_LOGIC;
        ddr3_ck_n : out STD_LOGIC_VECTOR(0 downto 0);
        ddr3_ck_p : out STD_LOGIC_VECTOR(0 downto 0);
        ddr3_cke : out STD_LOGIC_VECTOR(0 downto 0);
        ddr3_cs_n : out STD_LOGIC_VECTOR(0 downto 0);
        ddr3_dm : out STD_LOGIC_VECTOR(7 downto 0);
        ddr3_dq : inout STD_LOGIC_VECTOR(63 downto 0);
        ddr3_dqs_n : inout STD_LOGIC_VECTOR(7 downto 0);
        ddr3_dqs_p : inout STD_LOGIC_VECTOR(7 downto 0);
        ddr3_odt : out STD_LOGIC_VECTOR(0 downto 0);
        ddr3_ras_n : out STD_LOGIC;
        ddr3_reset_n : out STD_LOGIC;
        ddr3_we_n : out STD_LOGIC;                       
        phy_reset_n : out STD_LOGIC; 
        phy_mdc : out STD_LOGIC; 
        phy_mdio : inout STD_LOGIC; 
        phy_tx_clk : out STD_LOGIC; 
        phy_tx_ctrl : out STD_LOGIC; 
        phy_tx_data : out STD_LOGIC_VECTOR(3 downto 0); 
        phy_rx_clk : in STD_LOGIC; 
        phy_rx_ctrl : in STD_LOGIC; 
        phy_rx_data : in STD_LOGIC_VECTOR(3 downto 0);    
        fan_pwm : out STD_LOGIC;
        gpio_lcd : inout STD_LOGIC_VECTOR(6 downto 0);
        gpio_led : inout STD_LOGIC_VECTOR(3 downto 0);
        gpio_sw : inout STD_LOGIC_VECTOR(8 downto 0);
        iic_rstn : out STD_LOGIC;
        iic_scl : in STD_LOGIC;
        iic_sda : in STD_LOGIC;        
        hdmi_out_clk : out STD_LOGIC;
        hdmi_hsync : out STD_LOGIC;
        hdmi_vsync : out STD_LOGIC;
        hdmi_data_e : out STD_LOGIC;
        hdmi_data : out STD_LOGIC_VECTOR(23 downto 0);      
        spdif : out STD_LOGIC;  
        rx_clk_in_p : in STD_LOGIC;
        rx_clk_in_n : in STD_LOGIC;
        rx_frame_in_p : in STD_LOGIC;
        rx_frame_in_n : in STD_LOGIC;
        rx_data_in_p : in STD_LOGIC_VECTOR(5 downto 0);
        rx_data_in_n : in STD_LOGIC_VECTOR(5 downto 0);        
        tx_clk_out_p : out STD_LOGIC;
        tx_clk_out_n : out STD_LOGIC;
        tx_frame_out_p : out STD_LOGIC;
        tx_frame_out_n : out STD_LOGIC;
        tx_data_out_p : out STD_LOGIC_VECTOR(5 downto 0);
        tx_data_out_n : out STD_LOGIC_VECTOR(5 downto 0);
        gpio_txnrx : inout STD_LOGIC;
        gpio_enable : inout STD_LOGIC;
        gpio_resetb : inout STD_LOGIC;
        gpio_sync : inout STD_LOGIC;
        gpio_en_agc : inout STD_LOGIC;
        gpio_ctl : inout STD_LOGIC_VECTOR(3 downto 0);
        gpio_status : inout STD_LOGIC_VECTOR(7 downto 0);
        spi_csn : out STD_LOGIC;
        spi_clk : out STD_LOGIC;
        spi_mosi : out STD_LOGIC;
        spi_miso : in STD_LOGIC
);
    END COMPONENT;
 
begin
    
    uBlaze : System_Top
    PORT MAP (    
        sys_rst => sys_rst,
        sys_clk_p => sys_clk_p,
        sys_clk_n => sys_clk_n,        
        uart_sin => uart_sin,
        uart_sout => uart_sout,        
        ddr3_addr => ddr3_addr,
        ddr3_ba => ddr3_ba,
        ddr3_cas_n => ddr3_cas_n,
        ddr3_ck_n => ddr3_ck_n,
        ddr3_ck_p => ddr3_ck_p,
        ddr3_cke => ddr3_cke,
        ddr3_cs_n => ddr3_cs_n,
        ddr3_dm => ddr3_d,
        ddr3_dq => ddr3_dq,
        ddr3_dqs_n => ddr3_dqs_n,
        ddr3_dqs_p => ddr3_dqs_p,
        ddr3_odt => ddr3_odt,
        ddr3_ras_n => ddr3_ras_n,
        ddr3_reset_n => ddr3_reset_n,
        ddr3_we_n => ddr3_we_n,        
        phy_reset_n => phy_reset_n,
        phy_mdc => phy_mdc,
        phy_mdio => phy_mdio,
        phy_tx_clk => phy_tx_clk,
        phy_tx_ctrl => phy_tx_ctrl,
        phy_tx_data => phy_tx_data,
        phy_rx_clk => phy_rx_clk,
        phy_rx_ctrl => phy_rx_ctrl,
        phy_rx_data => phy_rx_data,        
        fan_pwm => fan_pwm,        
        gpio_lcd => gpio_lcd,
        gpio_led => gpio_led,
        gpio_sw => gpio_sw,        
        iic_rstn => iic_rstn,
        iic_scl => iic_scl,
        iic_sda => iic_sda,        
        hdmi_out_clk => hdmi_out_clk,
        hdmi_hsync => hdmi_hsync,
        hdmi_vsync => hdmi_vsync,
        hdmi_data_e => hdmi_data_e,
        hdmi_data => hdmi_data,        
        spdif => spdif,        
        rx_clk_in_p => rx_clk_in_p,
        rx_clk_in_n => rx_clk_in_n,
        rx_frame_in_p => rx_frame_in_p,
        rx_frame_in_n => rx_frame_in_n,
        rx_data_in_p => rx_data_in_p,
        rx_data_in_n => rx_data_in_n,        
        tx_clk_out_p => tx_clk_out_p,
        tx_clk_out_n => tx_clk_out_n,
        tx_frame_out_p => tx_frame_out_p,
        tx_frame_out_n => tx_frame_out_n,
        tx_data_out_p => tx_data_out_p,
        tx_data_out_n => tx_data_out_n,       
        gpio_txnrx => gpio_txnrx,
        gpio_enable => gpio_enable,
        gpio_resetb => gpio_resetb,
        gpio_sync => gpio_sync,
        gpio_en_agc => gpio_en_agc,
        gpio_ctl => gpio_ctl,
        gpio_status => gpio_status,        
        spi_csn => spi_csn,
        spi_clk => spi_clk,
        spi_mosi => spi_mosi,
        spi_miso => spi_miso
    );
end Behavioral;

 

Untitled.jpg

 


---------------------------------------------------------------------------------------------------
From Clock:  rx_clk
  To Clock:  rx_clk

Setup :           11  Failing Endpoints,  Worst Slack       -0.303ns,  Total Violation       -1.331ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.052ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.146ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) :        -0.303ns  (required time - arrival time)
  Source:                 i_system_wrapper/system_i/axi_ad9361/inst/i_dev_if/tx_p_data_n_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by rx_clk  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            i_system_wrapper/system_i/axi_ad9361/inst/i_dev_if/g_tx_data[2].i_tx_data/i_tx_data_oddr/D2
                            (rising edge-triggered cell ODDR clocked by rx_clk  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             rx_clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.000ns  (rx_clk rise@4.000ns - rx_clk rise@0.000ns)
  Data Path Delay:        3.585ns  (logic 0.379ns (10.572%)  route 3.206ns (89.428%))
  Logic Levels:           0 
  Clock Path Skew:        0.024ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.436ns = ( 8.436 - 4.000 )
    Source Clock Delay      (SCD):    4.578ns
    Clock Pessimism Removal (CPR):    0.166ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock rx_clk rise edge)     0.000     0.000 r 
    D18                                               0.000     0.000 r  rx_clk_in_p
                         net (fo=0)                   0.000     0.000    i_system_wrapper/system_i/axi_ad9361/rx_clk_in_p
    D18                  IBUFDS (Prop_ibufds_I_O)     0.890     0.890 r  i_system_wrapper/system_i/axi_ad9361/inst/i_dev_if/i_clk/i_rx_clk_ibuf/O
                         net (fo=1, routed)           2.034     2.924    i_system_wrapper/system_i/axi_ad9361/inst/i_dev_if/i_clk/clk_ibuf_s
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.082     3.006 r  i_system_wrapper/system_i/axi_ad9361/inst/i_dev_if/i_clk/i_clk_gbuf/O
                         net (fo=7551, routed)        1.572     4.578    i_system_wrapper/system_i/axi_ad9361/l_clk
    SLICE_X115Y220                                                    r  i_system_wrapper/system_i/axi_ad9361/inst/i_dev_if/tx_p_data_n_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X115Y220       FDRE (Prop_fdre_C_Q)         0.379     4.957 r  i_system_wrapper/system_i/axi_ad9361/inst/i_dev_if/tx_p_data_n_reg[2]/Q
                         net (fo=1, routed)           3.206     8.163    i_system_wrapper/system_i/axi_ad9361/dev_l_dbg_data[2]
    OLOGIC_X0Y220        ODDR                                         r  i_system_wrapper/system_i/axi_ad9361/inst/i_dev_if/g_tx_data[2].i_tx_data/i_tx_data_oddr/D2
  -------------------------------------------------------------------    -------------------

                         (clock rx_clk rise edge)     4.000     4.000 r 
    D18                                               0.000     4.000 r  rx_clk_in_p
                         net (fo=0)                   0.000     4.000    i_system_wrapper/system_i/axi_ad9361/rx_clk_in_p
    D18                  IBUFDS (Prop_ibufds_I_O)     0.850     4.850 r  i_system_wrapper/system_i/axi_ad9361/inst/i_dev_if/i_clk/i_rx_clk_ibuf/O
                         net (fo=1, routed)           1.926     6.776    i_system_wrapper/system_i/axi_ad9361/inst/i_dev_if/i_clk/clk_ibuf_s
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.078     6.854 r  i_system_wrapper/system_i/axi_ad9361/inst/i_dev_if/i_clk/i_clk_gbuf/O
                         net (fo=7551, routed)        1.583     8.436    i_system_wrapper/system_i/axi_ad9361/l_clk
    OLOGIC_X0Y220                                                     r  i_system_wrapper/system_i/axi_ad9361/inst/i_dev_if/g_tx_data[2].i_tx_data/i_tx_data_oddr/C
                         clock pessimism              0.166     8.602   
                         clock uncertainty           -0.035     8.567   
    OLOGIC_X0Y220        ODDR (Setup_oddr_C_D2)      -0.707     7.860    i_system_wrapper/system_i/axi_ad9361/inst/i_dev_if/g_tx_data[2].i_tx_data/i_tx_data_oddr
  -------------------------------------------------------------------
                         required time                          7.860   
                         arrival time                          -8.163   
  -------------------------------------------------------------------
                         slack                                 -0.303   


 

Message was edited by: Nick LaBianco

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