AD9268 datasheet (page 9) contains following information.
CLK Pulse Width High (tCH) has min/max specs, while CLK Period—Divide-by-1 Mode (tCLK) has only min spec. Datasheet doesn't contain any clock duty cycle specifications.
My clock source give me 40 MHz LVDS signal with 50% duty cycle. It gives me 12.5 ns of tCH (which is out of specs) and 25 ns of tCLK.
So, could I use 40 MHz clock signal with 50% duty cycle for clocking AD9268?
Could 40 MHz clock signal with 16% duty cycle be used for clocking AD9268?
Could I also use AD9513 for clocking AD9268 at 40 MHz?
Thank you in advance.