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Obtaining the desired rx_clk_in in the FPGA

Question asked by ofont on Nov 5, 2014
Latest reply on Nov 13, 2014 by dpu

Hi,


We are using the FPGA reference design for the FMCOMMS3 board, in combination with a ZC706. We have the AD9361 configured to work in the 2tx2rx mode. According to https://ez.analog.com/message/159226#159226, the rx_clk_in  clock signal runs at 4x the sample-rate (i.e., if the baseband sampling frequency is set at 1.92 MHz, the clock that will be received in the FPGA runs at 7.68 MHz). We have some questions regarding this:


  1. Is this 4x times relation (hardware-)fixed in the 2tx2rx mode? Or is there a way to modify this by tuning the FIR/HB interpolation factors? (e.g., instead of the default 2x FIR interpolation factor, force a x4 interpolation in order to receive a 15.36 MHz clock – from rx_clk_in – with a 1.92 Mhz datarate).
  2. If the 4x times relation cannot be modified, and focusing only in the DAC path, is there a way to move part of the interpolation to the FPGA area (e.g., through a Xilinx FIR IP) and configure the FIR/HB stages accordingly? More specifically, and continuing with the previous example, if it is applied a x2 interpolation in the FPGA area (i.e., the baseband sampling frequency is still 1.92 MHz, but the FIR returns the samples at 3.84 MHz), is it possible to configure the FIR/HB stages to accept a datarate of 3.84 MHz, thus forcing rx_clk_in to run at 15.36 MHz, but still producing a signal with a BW of 1.4 MHz (i.e., the one corresponding to 1.92 MHz baseband sampling frequency).


We have tried to play with different configurations of the FIR/HB (i.e., by using the AD9361 filter-design wizard), but it seems that no matter what we do, the FIR is always configured to provide a x2 interpolation (which, we guess, results in a rx_clk_in running at 4x the baseband sampling frequency).


Thank you very much in advance.


Oriol

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