I am working with a BF547 that has DDR SDRAM. I have an MDMA transfer that periodically occurs to move a small chunk of data from external DDR SDRAM into L1 data. This transfer has a critical real-time deadline that is top priority in the system.
There is also an ATAPI DMA transfer with destination memory in the same bank of external DDR SDRAM that the MDMA transfer uses for its source address. These two DMA transfers are not coupled and will overlap. Several MDMA transfers happen over the time span of one ATAPI DMA transfer. The ATAPI transfer is a single long DMA transaction.
My issue is that when the ATAPI transfer is active, the MDMA transfer takes about 1.5x to 2.0x longer than otherwise. I believe this is due to DEB arbitration. The ATAPI controller is tied to DMAC0, so there are no MDMA transfers that can win that arbitration.
I have tried using an MDMA channel on DMAC1 and then setting the bit in EBIU_DDRQUE to ensure that all DEB1 transfers are always urgent, but that did not help and the DEB is turned around just as often. I speculate this did not help because the ATAPI transfer will also go urgent as its FIFO drains, and so it will still win.
Is there any way I can force the MDMA to beat out the ATAPI DMA? I don't mind the ATAPI transfer stretching out because the interface supports flow control via a pause mechanism. Another solution would be if there is a way I can seamlessly force the ATAPI controller into a "pause" state before I initiate the MDMA transfer, but I do not see how that is possible.
I appreciate any thoughts on this topic.