In the Zynq hdmi reference hdl design for the Xilinx ZC706 platform, what is the input frequency the component named "axi_hdmi_clkgen".
I was able to get everything to build, but the script had trouble connecting this clock input on vivado 14.3. I tried to hook it up to the 200 Mhz system clock using the native board interface connection of the ZC706, but that produces an internal error deep down in the core. I think it does not like the differential pair from that clock. I succeeded in hooking up 50 mhz output from the PS, but this is probably not the right clock.
What clock is meant to go on the clk input of this component if you are using the ZC706 part?