Customer have a specific query that you may (already) have an answer to this. Please can you advise. the below (a) and (b)
My expectation is that for (a) it's not an issues and it can be done. For (b) I believe, if hardware coding and timing are done right/correctly, and using the buffer indication status these issues are avoidable. Please advise (or correlate).
(a) First question – If we were using the FMCOMMS5, is the LIBIIO/ip core flexible enough to allow streaming of 2bit IQ data from 3 channels at once into memory ready for us to stream out to hard drive? So the data DMA’d into the processor memory would be a continuous stream of 12-bit values comprising of 2bit quantised IQ for the 3 channels.
(b) Second question – In our existing system, we implement a large 2 second FIFO in the FPGA to make sure that no samples are lost during record or playback due to disk access or other interruptions. From the block diagram cf_ad9361_zc706_bd.jpg it looks as though the processor DDR is used for buffering so there will be some latency between sampling and the data getting stored in DDR. Surely this means that samples could be lost?