I'm trying to understand AD9915 parallel write timing according to datasheet page 33:
There is "t_ASU" (adr setup to WR active) which is measured from ADR bus change to WR HIGH-to-LOW transition.
This seems valid.
Then, there is "t_DSU" (data setup to WR active). In Figure 47, this is measured from DATA bus change to WR LOW-to-HIGH transition.
Is this correct? If yes, why is it not called "data setup to WR inactive?"
Also, if t_WR is 10.5 seconds, how can the bus be operated at 200 MBytes/s (page 29, 16 bit mode)? I'd see the limit at 190 MBytes/s...?